Job Description

Meta is hiring ASIC Design Verification Manager within the Infrastructure organization. We are looking for individuals with experience in managing medium to large Design Verification teams to build IP and System On Chip (SoC) for data center applications. As a Design Verification Manager, you will be supporting a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
ASIC Engineering Manager, Design Verification Responsibilities
  • Manage an ASIC design verification team responsible for various processing blocks in a SOC
  • Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure
  • Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams
  • Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts
  • Contribute to and drive development of and maintain overall silicon strategy aligned to corporation’s Long Range Plan objectives
  • Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing
  • Identify candidates, hire, schedule, support and train a team of ASIC engineers in order to develop products on time and on budget
  • Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers
  • Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs
  • Define, implement and maintain key performance indicators (KPI) for areas of responsibility
  • Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors
Minimum Qualifications
  • Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
  • Track record of first-pass success in ASIC Development
  • B.S. or M.S. degree in Computer Engineering or Electrical Engineering
  • Experience working across multiple projects and adjusting priorities in partnership with stakeholders
  • 10+ years experience managing ASIC/SoC design verification teams at the Director or Manager level
  • Experience managing and delivering UVM constrained random test benches
  • Experience with interpreting functional specs and creating comprehensive test plan
Preferred Qualifications
  • Experience with C/C++ based testbenches, DPI and SystemC
  • Experience with Formal verification and SVA
  • Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip and with performance verification
  • Knowledge of video coding standards, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework

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