Job Description
Duration: 12+ Months
Location: Sunnyvale, CA, United States (Need Locals)
Responsible for power validation plan development, execution and sign-off:
• Identify and communicate technical risks related to the project to the stakeholders
• Plan, organize, and oversee silicon bring-up and validation activities across multiple SoCs
• Understands system HW/SW/FW component as a whole and drives test execution and debug with cross functional teams
• Lead lab debug, silicon bug repro, failure analysis, and failure report activities
• Work with cross-functional teams (i.e. architecture, IP, FW, EE, SoC, emulation, and product engineer teams) to enable tests and perform pre to post-si correlation
• Able to work in an agile environment, changing roadmaps, and be able to adapt validation plans based on changes
• Power and performance modeling or DV (C, system C, system Verilog, or matlab)
• Strong DV background (test plan development, test writing, UVM) with Emulation
• Experience with low power verification (UPF)
Skills:
1) post Silicon Validation for Power and Performance
2) Experience in running emulation base P2Px
3) Python or C coding experience
4) Architectural knowledge of CPU
Education:
-Electrical and Computer Engineering (bachelor’s required, master’s strongly preferred)
